Design and simulation of hybrid SET-CMOS logic inverter using macro-model technique
Título del documento: Design and simulation of hybrid SET-CMOS logic inverter using macro-model technique
Revista: Revista mexicana de física
Base de datos: PERIÓDICA
Número de sistema: 000460629
ISSN: 0035-001X
Autores: 1
1
1
1
Instituciones: 1Cadi Ayyad University, Faculty of Sciences, Marrakech. Marruecos
Año:
Periodo: Nov-Dic
Volumen: 68
Número: 6
País: México
Idioma: Inglés
Tipo de documento: Artículo
Enfoque: Analítico, teórico
Resumen en inglés The single-electron transistor (SET) is one of the state-of-the-art devices that can offer high operating speed with ultra-low power consumption. The SET macro-modeling, can be used for the simulation of a SET-CMOS logic circuit. In this work, we develop a new hybrid, SET-CMOS logic inverter macro-model whose effect is very useful in VLSI circuits design. All simulations are performed using the SIM-SCAPE environment of MATLAB SIMULINK. This architecture has been realized by implementing the NMOS logic of the conventional inverter with a SET macro-model. The simulation results show that the hybrid structure offers better performance. Indeed, the designed circuit is able to operate at room temperature
Disciplinas: Física y astronomía,
Física,
Transistor de un solo electrón
Palabras clave: Macromodelos,
Simscape,
Inversor lógico,
Lógica híbrida SET-CMOS
Keyword: Physics,
Single electron transistor (SET),
Macro-modeling,
Simscape,
Logic inverter,
Hybrid SET-CMOS logic
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