Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm



Título del documento: Cell Assignment in Hybrid CMOS/Nanodevices Architecture Using a PSO/SA Hybrid Algorithm
Revista: Journal of applied research and technology
Base de datos: PERIÓDICA
Número de sistema: 000373894
ISSN: 1665-6423
Autores: 1
1
1
Instituciones: 1King Fahd University of Petroleum & Minerals, Center for Communications and IT Research, Dhahran. Arabia Saudita
Año:
Periodo: Oct
Volumen: 11
Número: 5
Paginación: 653-664
País: México
Idioma: Inglés
Tipo de documento: Artículo
Enfoque: Experimental, aplicado
Resumen en inglés In recent years, substantial advancements have been made in VLSI technology. With the introduction of CMOL (Cmos\nanowire\MOLecular Hybrid), higher circuit densities are possible. In CMOL there is an additional layer of nanofabric on top of CMOS stack. Nanodevices that lie between overlapping nanowires are programmable and can implement any combinational logic using a netlist of NOR gates. The limitation on the length of nanowires put a constraint on the connectivity domain of a circuit. The gates connected to each other must be within a connectivity radius; otherwise an extra buffer is inserted to connect them. Particle swarm optimization (PSO) has been used in a variety of problems that are NP-hard. PSO compared to the other iterative heuristic techniques is simpler to implement. Besides, it delivers comparable results. In this paper, a hybrid of PSO and simulated annealing (SA) for solving the cell assignment in CMOL, an NP-hard problem, is proposed. The proposed method takes advantage of the exploration and exploitation factors of PSO and the intrinsic hill climbing feature of SA to reduce the number of buffers to be inserted. Experiments conducted on ISCAS'89 benchmark circuits and a comparison with other heuristic techniques, are presented. Results showed that the proposed hybrid algorithm achieved better solution in terms of buffer count in reasonable time
Disciplinas: Ingeniería,
Ciencias de la computación
Palabras clave: Ingeniería electrónica,
Nanoalambres,
Microcircuitos,
Optimización combinatoria,
Heurística híbrida
Keyword: Engineering,
Computer science,
Electronic engineering,
Nanowires,
Microcircuits,
Combinatorial optimization,
Hybrid heuristics
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