| Revista: | Superficies y vacío |
| Base de datos: | PERIÓDICA |
| Número de sistema: | 000404719 |
| ISSN: | 1665-3521 |
| Autors: | Coyotl Mixcoatl, Felipe1 Torres Jacome, Alfonso1 |
| Institucions: | 1Instituto Nacional de Astrofísica, Optica y Electrónica, Tonantzintla, Puebla. México |
| Any: | 2004 |
| Període: | Dic |
| Volum: | 17 |
| Número: | 4 |
| Paginació: | 17-22 |
| País: | México |
| Idioma: | Inglés |
| Tipo de documento: | Artículo |
| Enfoque: | Analítico |
| Resumen en inglés | Latchup is a parasitic effect in CMOS technology, this is a PNPN parasitic structure formed by at least two coupled bipolar transistors. When a transitory voltage/current overshoot/undershoot at a input/output node occurs, PNPN structure can be turned on and a low impedance path between VDD and VSS can be formed. This low impedance state can produce either a momentary or a permanent loss of circuit functioning. In modern processes there are several techniques to reduce latchup in CMOS, some of them are the use of an epi layer, retrograde wells, SOI, deep trenches, etc. to spoil or decouple the parasitic bipolar transistors. Although such techniques can solve the latchup problem, they increase the cost of production. Thus, the bulk CMOS processes are still used. In this work an analysis of the latchup phenomena with the use of guard ring structures in order to prevent the latchup effect is made. Several structures have been analyzed with SSUPREM4 and S-PISCES with and without guard rings. The results show an increase in the holding voltage when guard ring structures are used. These structures will be fabricated in a 0.8 µm twin-well silicided bulk CMOS process in the Microelectronics Laboratory at INAOE |
| Disciplines | Física y astronomía, Ingeniería |
| Paraules clau: | Física, Ingeniería electrónica, Circuitos integrados, Semiconductores, Enclavado, Circuitos electrónicos |
| Keyword: | Physics and astronomy, Engineering, Physics, Electronic engineering, Integrated circuits, Semiconductors, Latch-up, Electronic circuits |
| Text complet: | Texto completo (Ver PDF) |
